View CA3126_399738.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

May 1999
CT T ODU MEN E PR PLACE -7747 T 2 OLE RE 0-44 OBS ENDED 1-80 .com MM ications arris l ECO h NO R ntral App entapp@ c Ce : Call or email
CA3126
TV Chroma Processor
[ /Title (CA31 26) /Subject (TV Chrom a Processor) /Autho r () /Keywords (Harris Semiconductor, TV chroma processor, subcarrier regeneration, ntsc, acc, overload detector, keyed chroma output, color processor, industrial
Features
* Phase Locked Subcarrier Regeneration Utilizes Sample-and-Hold Techniques * Automatic Chrominance Control (ACC)/Killer Detector Employs Sample-and-Hold Techniques * Supplementary ACC with an Overload Detector to Prevent Oversaturation of this Picture Tube * Sinusoidal Subcarrier Output * Keyed Chroma Output * Emitter Follower Buffered Outputs for Low Output Impedance * Linear DC Saturation Control
Description
The Harris CA3126 is a monolithic silicon integrated circuit designed for TV chroma processing and is ideally suited for NTSC color graphic applications that require subcarrier regeneration of the color burst signal.
Part Number Information
PART NUMBER CA3126E CA3126M1 TEMP. RANGE (oC) -40 to 85 -40 to 85 PACKAGE 16 Ld PDIP 20 Ld SOIC PKG. NO. E16.3 M20.3
Applications
* TV/CATV Receiver Circuits * NTSC Color Decoder/Processor * Computer Graphics Subcarrier Regenerator * Timing Reference for Frame Grabbers * DSP Clock Timing Reference Source
Pinouts
CA3126 (PDIP) TOP VIEW CA3126 (SOIC) TOP VIEW
CHROMA IN AFPC FILTER + AFPC FILTER RF BYPASS GROUND VCO OUT VCO IN CARRIER OUT
1 2 3 4 5 6 7 8
16 CHROMA GAIN CONT. 15 CHROMA OUT 14 ZENER REF 13 OVERLOAD DET.
CHROMA IN AFPC FILTER + NC AFPC FILTER RF BYPASS
1 2 3 4 5 6 7 8 9
20 CHROMA GAIN CONT. 19 CHROMA OUT 18 17 16 15 14 13 12 NC ZENER REF OVERLOAD DET. V+ ACC + ACC HORIZ. KEY IN
12 V+ GROUND 11 ACC+ VCO OUT 10 ACC9 HORIZ. KEY IN VCO IN NC
NC 10
11 CARRIER OUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1999
File Number
860.5
8-33
CA3126
Absolute Maximum Ratings
DC Supply Voltage (V+ to GND) (Note 1). . . . . . . . . . . . . . . . . 13.2V DC Current: Into V+ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38mA Into Zener Reference Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA DC Voltage (Horizontal Key In) Negative Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V Positive Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum Junction Temperature (Plastic Packages) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. This rating does not apply when using the internal zener reference in conjunction with an external pass transistor. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, Chroma Gain Control at maximum position for all tests except as noted. Electrical specifications referenced to test circuit. SWITCH POS. S1 S2 VCHROMA INPUT TP1 MIN TYP MAX UNITS
PARAMETER
TERMINAL, MEASUREMENT AND SYMBOL
DC ELECTRICAL SPECIFICATIONS Voltage Regulator Supply Current V12 I12 2 2 2 2 0 0 10.1 16 11.2 25 12.1 38 V mA
SWITCHING ELECTRICAL SPECIFICATIONS (Note 3) Pull-In Range (Note 4) Oscillator Output 100% Chroma Output Overload Detector Minimum Chroma Output (Note 5) 200% Chroma Output 20% Chroma Output Kill Level NOTES: 3. Except for pull-in range testing, tune oscillator trimmer capacitor for free running frequency of 3.579545MHz 10Hz. 4. Set Switch 1 to Position 2, detune oscillator 250Hz, set Switch 1 to Position 1, and check for oscillator pull-in. 5. Set Chroma Gain Control to minimum position (CCW). V8 V8 V15 V15 V15 V15 V15 VTP1 (Note 6) 2 1 1 1 2 2 2 1 2 0.5VP-P 0 0.5VP-P 0.5VP-P 0.5VP-P 1VP-P 0.1VP-P Vary 250 0.6 1.4 0.4 1.0 2.7 0.7 20 Hz VP-P VP-P VP-P mVP-P % of 100% Reading mVP-P
1 1 1
2 2 2
70 40 5
100 -
140 105 60
8-34
CA3126 Test Circuit
+24V 10k 270
VREG
2N2102 0.05F
3.9k CW 47k 10k CCW CHROMA GAIN CONTROL 1F 16 15 14
1
2 S2 0.01F 1F 13 12 11 10 9 0.02F I 0.02F 2k
OSCILLOSCOPE
CA3126
1 0.01F 2.45k TP1 S1 1 CHROMA INPUT SIGNAL 2
2 2 k 0.01F 0.1F
3
4
5
6
7
8 0.01F
680 0.01F 0.01F 10pF NPO XTAL 3.579545MHz 20pF N750 33pF N750 SUBCARRIER OUTPUT
COUNTER
50
VARIABLE ATTENUATOR
TEST SIGNAL GENERATOR
BURST SYNC.
KEY PULSE PULSE GENERATOR
2.5s
63.5s 3.579545MHz 4s VCHROMA 0.46VCHROMA 1.0VPEAK (MIN) 5s CENTERED ON BURST
Pin numbers refer to the PDIP package. (A) Chroma input signal (B) Key pulse input signal
(A)
BURST
(B)
8-35
CA3126 Block Diagram
TV CHROMA PROCESSOR
AFPC FILTER 1.0F 2k RF BYPASS 0.01F 4 SIGNAL SAMPLE AND HOLD AFPC DET. BIAS SAMPLE AND HOLD 0.01F
0.01F CRYSTAL FILTER 20pF 7 680 33pF
2
3
6
10pF CARRIER OUTPUT
DC CONTR. BALANCED SHIFTER
VCO
AMPL.
8 0.01F
SUPPLY VOLTAGE +24V
SHIFTER
CHROMA INPUT 2.45k 0.01F TO TERM. 12 CW 10 k CCW CHROMA INPUT 1 FIRST CHROMA AMPL. ATTENUATOR SECOND CHROMA AMPL. +/4 SHIFTER INTERN. REF. OVERLOAD DETECTOR
-/4
AMPL. LIMIT 13
270
10k
COUPLING NETWORK
12 +11.2V 0.05 F 15
2N2102 (NOTE 6) 0.01 F (NOTE 6)
CHROMA OUTPUT
3.9k BIAS CONTROL KILLER AMPL.
CHROMA GAIN CONTROL 16 50k 2F 1.2k KILLER FILTER
ZENER REF.
14
DELAY BIAS SIGNAL SAMPLE AND HOLD ACC DET. BIAS SAMPLE AND HOLD DELAY BIAS 0V 5s WIDTH HORIZONTAL KEY INPUT
ACC AMPL.
BALANCEUNBALANCE TRANSLATOR
KEYER
9 2k
GND
5
CA3126 10 0.01F 1F ACC FILTER 11 0.01F
NOTES: 6. Optional design features. 7. Pinout numbers refer to the PDIP package.
8-36
CA3126 Schematic Diagram
4 RF BYPASS A
AFPC DETECTOR FIRST CHROMA AMPLIFIER
Q71 Q9 R1 300 R2 700 R60 1.5K R4 300 R5 700 Q50 R7 500 R6 500 R3 250 Q3 R10 1.6K R9 500 D1 Q5 Q4 R12 1K Q7 R11 1.3K C3 5pF R14 2.1K C1 10pF Q51 Q52 Q10
SINGLE SAMPLE AND HOLD
R13 4K Q53 R17 2K Q54 R15 700 R16 12K Q11 Q12
B C D
R20 5K E
Q1
Q2
Q8
Q13
1 CHROMA INPUT
R19 12K Q6 R18 1K
F
R8 2.2K
G
SECOND CHROMA AMPLIFIER
ACC DETECTOR
R54 4K
SIGNAL SAMPLE AND HOLD
H I J K
R43 2.5K Q80 Q24 Q65 Q66 CHROMA OUTPUT 15 CHROMA GAIN CONTROL 16 R79 300 13 OVERLOAD DETECTOR Q22 Q25 R41 1K R40 330 D3 R42 8K Q23 R78 1K Q68 Q35 Q69 Q70 Q36
R57 2K Q72 R59 2K
L M N O P
Q33 Q31 Q32
Q34
Q67 R44 5K R77 750 Q20 Q27
ACC AMP.
Q29 R46 5K R48 2K
R49 700
ZENER REFERENCE
D1 Z2 Z3 R51 2K R50 5K Q30
Q47 R53 700
Q
KILLER AMP.
Q28 R47 5K R45 220
R52 1K
R55 3.5K R S T
OVERLOAD DETECTOR
5 GROUND (SUBSTRATE) ZENER 14 REFERENCE
NOTE: Pin numbers refer to the PDIP Package. Resistance values are in ohms.
8-37
CA3126 Schematic Diagram
2 A B C D Q59 R26 2K Q21 Q61 R28 390 Q18 E Q55 Q56 Q14 R25 1K R21 5K R23 8.2K Q60 Q15 C2 12pF R35 4.5K Q20 R34 R33 1K 1K R36 2.2K OSCILLATOR R39 500 D2 R38 1.5K R22 2K Q58 Q16 Q17 R30 430 R3 4K Q81 R29 390 BALANCED PHASE SHIFTER
(Continued)
XTAL FILTER 3 6 BIAS SAMPLE AND HOLD 7 CARRIER OUTPUT 8
AFPC FILTER
LIMITER AMPLIFIER
R27 3K Q62
Q64 Q57
R24 5K
R36 3K Q49 Q63 R37 2.2K
F
Q19 R32 750
G H I J K Q73 R63 100 R64 4.9K
BALANCE - UNBALANCE TRANSLATOR D6 R69 2K Q43 Q76 Q79
BIAS SAMPLE AND HOLD
POWER 12 SUPPLY +VCC
R71 5K
L M N Q40 Q41 Q37
Q44
Q45 10 ACC FILTER 11
O P Q39 R56 3.5K
Q46
R72 2K
R62 1.8K KEYER Q R61 2.94K Q74 Q38 R65 5K
Q75
R70 2.4K
Q77 R68 1.5K R67 1.5K Q42 R73 2.5K Q48 Z1 D5 D4 R74 1K R75 1.2K
R54 1K R S T 9
R66 2K
VOLTAGE REFERENCES HORIZONTAL KEYING INPUT
8-38
CA3126 Application Information
Circuit Description (Pin numbers refer to the DIP package.) The following paragraphs briefly describe the circuit operation of the CA3126 (shown in the Block Diagram and Schematic Diagram). A detailed description of the operation of various portions of the CA3126 is given in AN6247, "Application of the CA3126 Chroma-Processing lC Using Sample-and-Hold Techniques". The chroma input is applied to Terminal 1 through the desired band-shaping network. A 2,450 resistor should be placed in series with Terminal 1 to minimize oscillator pickup in the first chroma amplifier. This amplifier supplies signals to the second chroma amplifier and to the ACC and AFPC detectors. The first chroma amplifier is gain-controlled by the ACC amplifier. A horizontal keying pulse is applied to Terminal 9. This pulse must be present to ensure proper operation of the oscillator circuit. The subcarrier burst is sampled during the keying interval in the AFPC detector. The error voltage, produced at Terminal 2 and proportional to the burst phase, is compared to the quiescent bias voltage at Terminal 3 by the sample-and-hold circuitry. This "compared" voltage controls the phase- shifting network in the phase-locked loop. The operation of the AFPC loop is independent of any external adjustments or voltages except for an initial capacitor adjustment to set the free-running frequency. The regenerated oscillator signal at Terminal 8 is applied internally to the AFPC and ACC detectors through +45 and -45-degree phase-shifter networks to establish the proper phase relationship for these detectors. The ACC detector, which also samples the burst during the keying interval, produces a correction voltage proportional to the burst amplitude. The correction voltage is compared to the quiescent bias level using sample-and-hold circuitry similar to that used in the AFPC portion of the circuit. The "compared" voltage is applied internally to the ACC amplifier and killer amplifier. Because the amplifier gains and killer threshold are determined by the ratios of the internal resistors, these functions are independent of external voltages or controls. The attenuated chroma signal is fed to the second chroma amplifier, where the burst is removed by keyer action. The killer amplifier, the chroma gain control, and the overload detector control the action of the second chroma amplifier, whose gain is proportional to the dc voltage at Terminal 16. The overload detector (Terminal 13) receives a sample of the chroma output (Terminal 15) and detects the peak of the signal. The detected voltage is stored in an external capacitor connected to Terminal 16. This stored voltage on Terminal 16 affects the gain of the second chroma in the same manner as the chroma gain control. General Considerations The block diagram shown is typical of the type of circuit used in the practical application of the CA3126. Several items are critical for proper operation of the circuit. 1. A series resistor of approximately 2,450 (or high source impedance) must be used at the chroma input, Terminal 1. This high impedance minimizes pickup of unbalanced currents, particularly of the subcarrier oscillator signal. 2. When the overload detector is used, a large resistor (nominally 47,000) must be placed in series with Terminal 16 to set the required RC time constant. The same RC network series serves to set the killer time constant. 3. The setting of the free-running oscillator frequency requires the presence of the keying pulse. The free-running frequency will be erroneous if Terminal 1 is DC shorted during the setting operation because of the DC offset voltage introduced to the AFPC detector. 4. Care must be taken in PC board designs to provide reasonable isolation between the oscillator portion of the circuit (Terminals 6, 7, and 8) and the chroma input (Terminal 1). Overload Detector The overload detector accomplishes two purposes: 1. It prevents oversaturation due to low burst-to-chroma ratios. 2. It prevents overload conditions due to noise. Both of these conditions are discussed in more detail in AN6247. The extent to which the overload detector is used depends upon the individual receiver design goals. If greater than 0.5VP-P output is desired, the chroma output at Terminal 15 can be tapped to yield any desired degree of overload detector action. Chroma Gain Control The chroma gain control operates by varying the base bias on current source transistor Q25. To ensure proper temperature tracking of the chroma gain control, it is essential that the control be operated from a supply source derived from the reference voltage at Terminal 12. Because the control operates from a current source, chroma gain is much more predictable and far less temperature sensitive than controls that steer current by means of a differential amplifier. The typical chroma gain characteristic for the CA3126 is shown in Figure 1.
CHROMA OUTPUT (% OF MAX. VALUE)
TA = 25oC, CHROMA INPUT = 0.5VP-P 100
80
60
40
20
0
20
40
60
80
100
120
140
VOLTAGE AT TERMINAL 16 (% OF V12)
FIGURE 1. CHROMA GAIN CONTROL
Subcarrier Regenerator Oscillator The oscillator filter consists of a 3.579545MHz crystal, a 680 resistor, and a 10pF capacitor connected in series across Terminals 6 and 7. A 33pF capacitor, shunt connected from Terminal 7 to ground, rolls off higher order harmonics, thereby preventing oscillation at the crystal third-harmonic frequency. A
8-39
CA3126
CHROMA OUTPUT AMPLITUDE (% OF 25oC VALUE) CHROMA INPUT = 0.25VP-P , 3.58MHz CW SIGNAL 130 10 CHROMA OUTPUT PHASE (DEGREE OF DEVIATION FROM 25oC VALUE) 125
curve of the typical static phase error as a function of the freerunning oscillator frequency is shown in Figure 2. It should be noted that the slope of the curve determines the DC gain of the phase-locked loop, i.e., 40Hz per degree.
TA = 25oC
140
15
120 PHASE
5
STATIC PHASE ERROR (DEGREES)
6
110
0
4
100
AMPLITUDE
-5
2
90 80 -50
-10
0
-25
0
25
50
75
-15 100
-2
TEMPERATURE (oC)
-4 -300 -200 -100 0 100 200 300 OSCILLATOR FREE-RUNNING FREQUENCY (DEVIATION IN Hz FROM 3.579545MHz) 400
FIGURE 4. AMPLITUDE AND PHASE VARIATIONS OF CHROMA OUTPUT vs TEMPERATURE
FIGURE 2. STATIC PHASE ERROR
OSCILLATOR FREE-RUNNING FREQUENCY (DEVIATION IN Hz FROM 3.579545 MHz)
CHROMA INPUT = 0VP-P 100
Thermal Considerations The circuit of the CA3126 is thermally compensated to achieve the optimal operating characteristics over the normal operating temperature range of TV receivers. Figures 3 and 4 show the oscillator and chroma-output amplitudes and phases as a function of temperature (Terminals 8 and 15), respectively. Both the oscillator and chroma-output amplitudes and phases are measured relative to the chroma-input phase. The performance of the oscillator free-running frequency as a function of temperature is shown in Figure 5. All the temperature plots are characteristic of the test circuit with the indicated component types and values given.
OSCILLATOR AMPLITUDE (% OF 25oC VALUE) CHROMA INPUT = 0.25VP-P, 3.58MHz CW SIGNAL OSCILLATOR PHASE (DEGREE OF DEVIATION FROM 25oC VALUE)
50
0
-50
-100
-150 -50
-25
0
25
50
75
100
TEMPERATURE (oC) 110
FIGURE 5. VARIATION OF OSCILLATOR FREE RUNNING FREQUENCY vs TEMPERATURE
100
PHASE
0
90 AMPLITUDE 80 -5
70
60 -50
-25
0 25 50 TEMPERATURE (oC)
75
-10 100
FIGURE 3. AMPLITUDE AND PHASE VARIATIONS OF OSCILLATOR OUTPUT vs TEMPERATURE
8-40
CA3126
0.01F 0.01F +12V 0.01F 0.01F 1F 5pF-25pF 2k 680 INPUT FILTER 82pF 68pF TYP. 0.5VP-P 56 pF 6 XTAL 33pF 10pF 7 FSC 3.579545MHz SUBCARRIER OUTPUT (CW) VCO SUBCARRIER AMP 8 0.01F
12
4
3
2
L1 12H
L2 27H
500 2.4k
VCC
AFPC DET/FILT.
CA3126
COMPOSITE VIDEO/CHROMA INPUT 0.01F 1 FIRST CHROMA AMP CHROMA/ BURST-GATE SWITCH 2ND CHROMA AMP 15
ACC AMP 11.2V ZENER REF
ACC DET/FILT.
CHROMA O.L. DET KILLER AND GAIN CONT.
BURST KEYER AMP
14
5
10 1F
11
13
16
9 2k >1VPEAK 0V
0.01F
0.01F
NOTE: For Subcarrier Regenerator, the second chroma amp is not used; Pins 13,14, and 15 are not connected and pin 16 is grounded.
BURST KEY PULSE 4s (TYP), CENTERED ON BURST
FIGURE 6. TYPICAL APPLICATION OF THE CA3126 AS A SUBCARRIER REGENERATOR
8-41

▲Up To Search▲

Price & Availability of CA3126

	To Download CA3126 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .